Polishing process for producing damage free surfaces on semi-insulating silicon carbide wafers

ABSTRACT

A polishing mixture and related method of polishing a material wafer surface, such as silicon carbide, are disclosed. The polishing mixture comprises; an abrasive and an oxidizer mixed in an acidic solution. Alumina may be used as the abrasive and the polishing mixture may have a pH less than or equal to seven (7).

This application claims the benefit of U.S. provisional application60/629,409 filed Nov. 19, 2004, the subject of which is herebyincorporated by reference.

STATEMENT OF GOVERNMENT RIGHTS

Work related to the invention was done in performance of GovernmentContract No. DAAD19-02-1-0231. The government has certain rights in theinvention.

COLOR DRAWINGS

The patent or application file contains at least one drawing executed incolor. Copies of this patent or patent application with color drawingswill be provided by the Office upon request and payment of the necessaryfee.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Embodiments of the invention relate generally to surface treatments,such as those adapted for use in the polishing of a material surfaceuseful in the fabrication of semiconductor devices.

2. Description of Related Art

Silicon carbide (SiC) is used extensively as a semiconductor materialfor many applications. Semiconductor devices formed on a SiC substratehave the ability to operate at higher voltages and temperatures thanconventional devices formed on a silicon (Si) substrate. Indeed, formany high frequency, high temperature, high voltage, and/or hostileradiation environment applications, SiC is rapidly becoming thesemiconductor material of choice.

SiC may be grown in many different polytypes, but 6H and 4H polytypesare widely used in industry. The “H” in these polytype designationsrefers to a hexagonal crystal structure, and the “4” or “6” denotes thenumber of steps before replication of the structure. Polytypes may beoriented “on” or “off” a primary crystal axis.

Regardless of polytype, SiC may be doped with elements that increase ordecrease its resistivity. When SiC resistivity reaches levels greaterthan about 10⁵ ohm-cm, it is considered semi-insulating. However, onecurrent industry trend seeks to produce intrinsically puresemi-insulating SiC material which is not doped. The most commoncommercially available wafer types are 4H— and 6H—SiC, both conductiveand semi-insulating, as well as on axis and up to 8° off axis. Wafersformed from SiC are used as substrates supporting the fabrication ofsemiconductor devices.

The performance qualities exhibited by semiconductor devices formed on aSiC substrate are greatly influenced by the structural integrity andsmoothness of epitaxial films grown on the substrate. A smooth,defect-free surface is crucial to the epitaxial growth of high-qualitythin films. Numerous studies of epitaxially grown thin films on 4H— and6H—SiC substrate have shown that fabrication process induced defects inthe substrate surface, such as scratches and/or subsurface damageintroduced during lapping and polishing processes, are primarycontributors to unwanted polytype inclusions in the subsequently grownepitaxial films.

Unfortunately, the material properties of SiC that provide its desirablecharacteristics also present difficult challenges to putative surfacetreatment techniques. For example, SiC is extremely hard, possessing aMohs hardness of nine plus (9⁺). It is very chemically stable, andgenerally unaffected by exposure to acid or alkali at temperatures lessthan about 300° C.

Conventional surface treatments applied to SiC may be generallycategorized as mechanical polishing, chemical-mechanical polishing(CMP), and etching. Mechanical polishing techniques are characterized bythe use of very hard abrasives, such as diamond grit, applied to thesurface of a SiC wafer. While mechanical polishing effectively removessurface material, it often results in a rough and/or damaged wafersurface. Conventional etching techniques applied to SiC wafers areperformed at high temperature, and while potentially useful in thelocalized planarization of the wafer surface are ill-suited to globalplanarization objectives.

As a result of the deficiencies noted in mechanical polishing andetching techniques, significant research has been directed to improvingCMP techniques. CMP techniques generally combine mechanical polishingwith chemical etching to provide a wafer surface having decreasedoverall roughness and less damage to subsurface layers. In a recenttechnical paper, one conventional CMP method was proposed wherein aconcentrated colloidal silica slurry having high pH (e.g., a pH higherthan 10) was applied at elevated temperatures (e.g., 55° C.) to theSi-terminated surface of a SiC wafer. See, J. Electrochem. Soc. Vol.144, No. 6, June 1997, the subject matter of which is herebyincorporated by reference. Similalry, in patent document WO 2005/099388A2, the subject matter of which is hereby incorporated by reference,another conventional CMP method was proposed wherein a high pH (e.g., 8to 14) solution containing colloidal silica or alumina was used topolish an SI wafer.

Due to the hardness of SiC, multiple surface treatments or surfacetreatment cycles are often applied before an acceptable surface isobtained. Mechanical polishing using diamond grit remains the industrystandard, at least in the early stages (or cycles) of SiC surfacetreatment. Typical practice involves the slicing of SiC wafers from acrystalline boule using a wire saw having a fixed diamond abrasive or awire carrying a mixture of diamond and boron carbide grits in a slurrysolution. To remove the wafer surface damage resulting from the cuttingprocess, SiC wafers are fixed to a platen and then lapped and polishedwith a succession of smaller size diamond grits on a conventionalpolishing machine. This is typically a 4-step process beginning with a3-micron diamond grit, moving to a 1-micron diamond grit, and then to a0.25-micron diamond grit. The final polishing step is often aconventional CMP process using colloidal silica.

However, as will be seen in some additional detail by way of comparisonto embodiments of the invention, conventional surface treatmenttechniques simply do not work well—particularly when applied towide-bandgap material such as SiC. Among other deficiencies apparent inconventional surface treatment techniques, selective etching ofscratches and other surface defects may actually increase the overallroughness of a wafer surface. That is, conventional surface treatmenttechniques often remove equal amounts of material from the working wafersurface and scratches and other defects present in the working surface.Thus, scratches and surface defects are merely propagated down into thewafer surface by the conventional surface treatments. Worse still, someconventional surface treatments selectively etch the scratches andsurface defects to a greater degree than the working wafer surface,thereby deepening and/or expanding the scratch or defect.

A non-selective—relative to scratches and other surface defects formedin a wafer surface—surface treatment process is needed. At a minimum,the non-selective process should work on all major polytypes of SiC,including at least 6H and 4H polytypes, whether the SiC wafer is formedoff-axis and on-axis, and whether the SiC wafer is conductive orsemi-insulating in nature.

SUMMARY OF THE INVENTION

Embodiments on the invention provide a non-selective surface treatmentwell adapted to the polishing of material wafer surfaces, such as SiCwafers.

In one embodiment, the invention provides a process adapted to thetreatment of a material surface comprising; polishing the surface usinga polishing mixture, the polishing mixture comprising; an abrasive andan oxidizer mixed in an acidic solution having a pH equal to or lessthan 7.

In another embodiment, the invention provides a polishing mixture havinga pH equal to or less than 7 and comprising; an abrasive and an oxidizermixed with an acid and a solvent.

In yet another embodiment, the invention provides a process offabricating a semiconductor device comprising; polishing a surface of amaterial wafer using a polishing mixture and thereafter growing anepitaxial layer on the substrate, wherein the polishing mixture isnon-selective relative to scratches in the material wafer, has a pH of 7or less, and generally comprises one or more abrasives and an oxidizer.

BRIEF DESCRIPTION OF THE DRAWINGS

Several embodiments of the invention are described with reference to theattached color images. These images are identified as “figures” withinthe description and are variously generated by well understood andconventionally interpreted imaging techniques, including TunnelingElectron Microscopy (TEM), Atomic Force Microscopy (AFM), PhotonBack-Scattering (PBS) measurements, and ZYGO Light Interferometery(ZYGO).

FIGS. 1A through 1D are related ZYGO images illustrating wafer surfacecharacteristics through a sequence of polishing cycles using oneembodiment of the invention.

FIGS. 2 a through 2D are related ZYGO images illustrating wafer surfacecharacteristics through a sequence of polishing cycles using aconventional CMP technique.

FIG. 3 is a TEM image of a wafer surface polished using a conventionalCMP technique.

FIG. 4 is a TEM image of a wafer surface polished using one embodimentof the invention.

FIGS. 5A and 5B are comparative AFM images, FIG. 5A showing aconventionally polished wafer surface and FIG. 5B showing a wafersurface polished using one embodiment of the invention.

FIGS. 6A and 6B are optical micrographs of epitaxial gallium nitride(GaN) layers respectively grown on a conventionally polished wafersurface and a wafer surface polished using one embodiment of theinvention.

FIGS. 7A through 7E are AFM images further illustrating the qualitativedifference between GaN layers grown on a conventional polished wafersurface and a wafer surface polished using one embodiment of theinvention.

FIG. 8 is an AFM image of a wafer surface after polishing using oneembodiment of the invention.

FIG. 9 is another AFM image of a wafer surface after conventionalpolishing.

FIGS. 10A and 10B are PBS measurement images comparatively illustratingthe subsurface damage for a conventionally polished wafer surface and awafer surface polished using one embodiment of the invention.

FIG. 11 is a TEM image illustrating a conventionally polished wafersurface.

FIG. 12 is a TEM image illustrating a wafer surface polished using oneembodiment of the invention.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

Embodiments of the invention will now be described. These embodimentsare presented as teaching examples. The actual scope of the invention isnot limited to only these examples, but is defined by the attachedclaims.

In one aspect, embodiments of the invention address the issue of errantpolishing selectivity noted above with respect to conventional polishingtechniques. That is, embodiments of the invention address theinadequacies associated with the etching selectivity of conventionalsurface treatment techniques in which scratches and other surfacedefects are etched to an equal or greater extent than the workingsurface of a wafer. In this context, the term “etch[ing]” is used togenerically describe any process removing material from any portion ofthe working surface of a wafer. The term “working surface” generallyidentifies a major wafer surface being treated or polished. Scratchesand other surface defects are generally characterized by surfaceprofiles having a vertical depth different from a desired plane for theworking surface.

In the context of conventional polishing techniques and equipment,within which embodiments of the invention may be readily incorporated,the axis through which force is applied to a wafer being polished istermed the “vertical” axis. An axis normal to the vertical axis istermed a “lateral” axis. Using this terminology convention, a scratchmay be said to have vertical depth into the working surface of a waferand lateral width across the plane of the working surface. These termsare, however, merely relative orientations and conveniently drawn tocurrent polishing techniques and equipment. Embodiments of the inventionare not limited by such descriptions of relative orientation (e.g.,vertical verses lateral).

The results of errant etching selectivity associated with, for example,conventional polishing techniques using colloidal silica will be furtherhighlighted for comparative purposes in the description that follows.Exemplary embodiments of the invention were applied to semi-insulatingSiC wafers to produce relatively defect-free working surfaces withrespect to conventional outcomes. The improved chemical-mechanicalpolishing (CMP) process provided by embodiments of the invention hasbeen developed such that it may be easily incorporated into existingfabrication lines (e.g., used with commercially available consumablesand equipment, as well as collaterally related techniques).

Throughout this description, the term “improved polishing process” isused to generally denote a surface treatment, or part of a surfacetreatment, incorporating one or more embodiments of the invention. Theterm “improved polishing process” also distinguishes conventionalpolishing process(es). The term “improved surface” is used to refer to aworking surface, such as one adapted for use as a semiconductorsubstrate, that has been treated using the improved polishing process.

In one embodiment, the invention provides an improved polishing processcharacterized by the provision and/or use of a polishing mixturecomprising an abrasive, an oxidizer, and an acid within a solvent. Thegeneral combination of acid and solvent may be replaced by the term“acidic solution” since at least some embodiments of the inventionprovide acid in sufficient quantity to reduce the pH of the polishingmixture to below seven (7), or alternatively below five (5). Acetic acidhas been successfully used in one embodiment to effectively lower thepolishing mixture pH, but other acids or acidic solutions may used forthis purpose.

In another embodiment of the invention the foregoing polishing mixtureis applied to the working surface of a material wafer.

The abrasive in the foregoing polishing mixture may comprise alumina.The abrasive may be formed from a single abrasive or a mixture of two ormore abrasives. In one embodiment of the invention, the abrasive has ahardness less than that of the material being polished.

By way of comparison, conventional CMP processes commonly use apolishing mixture having a much higher pH, typically at least a pH often (10). This high pH level is used to oxidize the working surface ofthe wafer being polished. To increase the material removal rate, hardabrasives, such as diamond may be applied to the conventional colloidalsilica CMP processes to remove the resulting oxide layer.

Embodiments of the improved polishing process are non-selective relativeto scratches and other defects in the working surface of a wafer, ascompared with conventional CMP processes. Thus, scratches are removed ata rate equal to or greater than the general rate of material removal forother portions of the working surface. This is true for applications ofthe improved polishing process to 6H— and 4H—SiC wafers—both doped andun-doped, as well as on-axis and off axis in nature. The rate ofmaterial removal provided by the improved polishing process is generallygreater than or equal to that provided by conventional CMP processes,such as those using colloidal silica. Thus, substantially defect-freewafer surfaces may be obtained by use of the improved polishing processwith reduced consumables and polishing time. Hence, the improvedpolishing process provides cost and time advantages over theconventional CMP processes.

This non-selective quality of the improved polishing process may befurther characterized in one embodiment of the invention as providing arelatively higher rate of material removal in the direction of thevertical axis of the wafer surface (i.e., the direction normal to theworking surface of the wafer) than in any lateral direction across thewafer surface. As a result, scratches and other surface defects areremoved. In contrast, conventional CMP processes have a relatively lowvertical rate of material removal and a relatively high lateral rate ofmaterial removal, and therefore tend to broaden and/or deepen scratchesand other defects present in a wafer surface.

Specific test examples, including exemplary applications of bothconventional CMP and improved polishing processes, are described belowwith reference to Tables 1, 2, and 3. Each of the test examples wasperformed using a commercially available SiC wafer. A single type oftest material was selected for comparative purposes, and SiC is aconvenient, practical choice for testing.

The improved polishing process may, however, be applied to wafers formedfrom materials other than SiC. For example, the improved polishingprocess may be used to treat a material surface comprising one or morematerials including a conducting material, an insulating material, adielectric or a semi-conducting material selected from a group ofmaterials including a metal, an oxide, a glass, an alloy, a carbide, anitride, diamond, a silicide, a chromide, ferride, a boride, a sulfide,a phosphide, silicon nitride, silicon nitride, aluminum nitride, galliumnitride, alumina-gallium nitride, indium-gallium nitride, Safire, Indiumphosphide, boron nitride, silicon, and silica, as well as and anyreasonable combination of such.

In at least one embodiment of the invention, the improved polishingprocess finds particularly useful application in the surface treatmentof wide band gap semiconductor material(s) such as those commonly usedas a substrate adapted to the formation of active semiconductor devicesand layers.

After polishing each test example, the wafer surface was variouslyimaged and/or evaluated using one or more of the following: TunnelingElectron Microscopy (TEM), Atomic Force Microscopy (AFM), ZYGO WhiteLight Interferometery (ZYGO), optical micrographs, and/or PhotonBack-Scattering (PBS) measurements. Additionally, for some testexamples, the growth of a gallium nitride (GaN) layer on the polishedwafer surface was used to further characterize the material propertiesof the wafer. From the foregoing, average roughness (Ra), root meansquare roughness (Rq), and peak-to-valley roughness (PV) for eachpolished wafer surface was determined.

Of note, evaluation of some test examples suggests that defect densitiesfor wafer surfaces polished using the improved polishing process can beequal to the intrinsic defect densities expected for native SiC.Further, the improved polishing process did not increase subsurfacedamage or the amount of dislocations present in the test examplematerials.

Table 1 below summaries various polishing mixtures and processconditions associated with selected test examples. Test example number(or run number) is indicated in the first column of Table 1. Of note,test example “0” corresponds to a conventional CMP process usingcolloidal silica.

For each test example following test example “0”, a polishing mixturesolution ratio is given in the second column of Table 1. Where colloidalsilica is used in the polishing mixture, its mixture ratio with water(i.e., the common solvent used the polishing mixtures applied to thetest example) is given. In test examples run using a polishing mixturewithout colloidal silica, the entry in column 2 is left empty (−). Next,in the third column, an abrasive additional to colloidal silica, whereused, is identified along with its volume concentration as a percentageof the polishing mixture (Conc.). Thereafter, in the fifth column, anoxidizer, if used, is identified along with its volume concentration asa percentage of the final polishing mixture.

The seventh column of Table 1 indicates a rotational speed for apolishing platen in revolutions per minute (RPM) during the testexample. The eighth column of Table 1 indicates the vertical forceapplied to the test example wafer during the polishing process. Theninth column indicates a polishing run time for the test example.

An initial roughness value (Ra-start—expressed in Angstroms (Å)),indicating an average roughness of the wafer surface before polishing isgiven next in column ten of Table 1. For comparison, an averageroughness value for each test example after polishing is also given(Ra-final) in the eleventh column of Table 1. Finally, an average rateof material removal (MRR) is expressed for each test example in μm ofmaterial per hour in the last column of Table 1. TABLE 1 SiO2 Run Ra Ra0.06 um Abrasive Force time (start) (final) MRR Run # H₂O Size/Type ConcQxidizer Conc RPM (PSI) (Hrs) (Å) (Å) (um/hr) 0 1/1 0.06 um SiO2 — SiO2— 140 5 8 7.5 44.5 0.06 1 1/1 1 um Al2O3  50% — — 140 5 8 10.1 50.0 0.252 1/1 1 um Al2O3  50% — — 140 5 8 8.8 40.13 0.16 3 1/1 2 um ZrO2  50% —— 140 5 8 9.9 42.8 0.00 4 — 0.5 um diamond 100% — — 120 5 5 Sawed 6.84.90 5 — 0.1 um diamond 100% — — 70 5 5 7.2 7.6 0.60 6 — 0.1 um diamond100% — — 20 5 8 8.1 7.3 0.25 7 1/1 0.1 um diamond  25% — — 120 5 4 6.815.4 0.94 8 1/1 0.1 um diamond  10% — — 120 5 8 4.5 17.6 0.56 9 1/1 0.1um diamond  25% — — 20 5 10 7.9 10.1 0.20 10 1/1 0.1 um diamond  10% — —20 5 10 7.5 5.5 0.60 11 1/1 0.1 um diamond  10% — — 20 5 6 7.7 14.6 0.5012 1/1 0.05 um  50% — — 120 5 8 7.6 38.7 0.06 diamond 13 1/1 0.05 um 50% — — 20 5 8 7.2 11.6 0.025 diamond 14 1/1 0.05 um  25% — — 120 5 87.6 19.8 0.06 diamond 15 1/1 0.05 um  25% — — 20 5 8 82 10.2 0.00diamond 16 1/1 — — NaOCl 50% 120 5 6 7.5 28.9 0.125 17 1/1 — — NaOCl 25%120 5 6 8.9 29.5 0.061 18 1/1 — — NaOCl 10% 20 5 6 5.2 17.1 0.073 19 1/1— — H2O2 50% 120 5 6 5.8 78.9 0.043 20 1/1 — — H2O2 25% 20 5 6 7.1 14.80.050 21 1/1 — — H2O2  3% 20 5 6 9.1 17.2 0.045 22 1/1 0.1 um diamond 10% NaOCl 10% 20 5 8 6.5 5.2 0.92 23 1/1 0.1 um diamond  10% H2O2  5%20 5 6 11.9 63.0 0.062 24 90/0% — — NaOCl 10% 20 5 6 7.5 15.5 0.11 2580/0% 0.1 um diamond  10% H2O2 10% 20 5 6 7.6 12.6 0.17 26 80/0% 0.1 umdiamond  10% NaOCl 10% 20 5 8 7.3 20.39 0.25 27 1/1 0.05 um  10% NaOCl10% 20 5 6 7.5 25.5 0.125 diamond

As may be seen from Table 1, only test examples 4, 6, 10, and 22 resultin only marginal improvement in the average roughness of the respectivewafer surface. Further, many of the test examples result in very lowrates of material removal (MRR).

Based on the test examples contained in Table 1, additional testexamples were investigated. Results from these additional test examplesare summarized in Table 2. In Table 2, a conventional CMP process using0.06 um colloidal silica (CS), as applied to a SiC wafer surface, isidentified as a baseline. Then, various oxidizer, abrasive, andoxidizer-plus-abrasive enhancements are made to the baseline process.Relative rates of material removal (MMR) are indicated, as are relativeeffects on final wafer surface roughness (Ra-final). Finally, an “etchedroughness” value (Ra-etched) is given for each variation. Etchedroughness is determined by conventional molten KOH testing for assessingsubsurface damage associated with the polished wafer surface.

Clearly, certain enhancements to the conventional CMP process involvingsome combinations of an oxidizer, colloidal silica, and variousadditional abrasive(s) provide dramatic improvements in the MMR andfinal roughness (Ra-final) of the wafer surface.

The addition of an oxidizer alone to the conventional colloidal silicabased CMP process resulted in only a small increase in MRR and increasedsurface roughness. Such enhancements also resulted in selective materialremoval relative to surface damage present in the wafer surface.

The addition of abrasive particles alone, wherein the particles aresofter than SiC but harder than SiO₂, resulted generally in no change tothe MRR, increased surface roughness, and selective material relative tosurface damage.

However, the addition of low concentrations of nano-diamond particles(near 0.1 μm) resulted in a higher MRR (e.g., a 10× increase overbaseline), low average surface roughness, and reduced selectivity ofmaterial removal in damaged surface regions. The combination of 0.1 μmdiamond with an oxidizer further increased MRR by 50%, (e.g., a 15×increase over baseline), low average surface roughness Ra, and reducedselectivity of material removal in damaged surface regions.

In the test examples noted in Table 1, when alumina abrasive particleswere used in a polishing mixture having a pH greater than seven (7),selective etching was observed. However, by reducing the pH to seven (7)or below, such as to approximately five (5), and adding an oxidizer,improved polishing results were obtained over the conventional CMPprocess. This was particularly true in embodiments of the inventionwhere the alumina comprised a “mixed phase alumina slurry” including,for example, a mixture of corundum and AlOOH or boehmite. In contrast,where a standard alumina abrasive comprising primarily alpha alumina (orcorundum) is used the polishing results are not equivalent to thoseobtained using the mixed phase alumina slurry. This result suggests insome embodiments of the invention that AlOOH may be acting as a chemicalcomponent and increasing the rate of surface oxidation therebyincreasing removal rate and reducing selectivity.

Summarizing the results of Table 2, oxidizer-enhanced polishingprocesses provide lower MRR and relatively high surface roughness.Further, decorated subsurface damage was noted. Abrasive-enhancedpolishing processes provide higher MRR, relatively high surfaceroughness, and continued decorated subsurface damage. Oxidizer/diamondabrasive-enhanced polishing processes provide much higher MRR,relatively low surface roughness, and reduced subsurface damage.However, it does not produce damage free surfaces as demonstrated by TEMobservations and may only be useful as a precursor to the improvedpolishing process. TABLE 2 MRR versus Ra final versus Ra etched versusProcess [μm/h] baseline [Å] baseline [Å] Ra final Baseline CMP = 0.06 μmcolloidal silica (CS) 0.060   1x 68.3 1x 70.3  +2.9% Oxidizer-enhancedCMP CS + NaOCl 0.125  2.1x 17.1  4.0x — CS + H₂O₂ 0.050 0.83x 14.8  4.6x— Abrasive-enhanced CMP CS + alumina 0.250  4.2x 40.1  1.7x 42.6  +6.2%CS + zirconia 0.160  2.7x 42.7  1.6x 39.4  −7.7% CS + 0.05 μm diamond0.063  1.1x 10.2  6.7x — CS + 0.1 μm diamond 0.060  1.0x 5.5 12.4x —(Oxidizer + Abrasive)-enhanced CMP CS + 0.1 μm diamond + NaOCl (for 6HSiC) 0.92   15x 5.2 13.1x 5.6  +7.7% CS + 0.1 μm diamond + NaOCl (for 4HSiC) 0.55  9.2x 5.3 12.9x 13.6  +157%

Table 3 below contains still further test example results variouslyillustrating improvements and adaptations consistent with one or moreembodiments of the invention. The test examples shown in Table 3 aregenerally characterized by the use of alumina (Al₂O₃) as an abrasive.For example, test example run # 28 was 40% solvent (e.g., water), 40%abrasive, and 20% oxidizer by volume. Of note, the polishing mixturesobtained by the test examples shown in Table 3 each possessed a pH offive (5) or less, and therefore did not require the addition of anyacid. This, however, may not be true for all possible variations of animproved polishing mixture consistent with one or more embodiments ofthe invention. Where desired or needful, the pH of the improvedpolishing mixture may be modified through the addition of acid. Forexample, acetic acid may be added in small quantities to reduce the pHof the improved polishing mixture to around five (5). The test examplesshown in Table 3 resulted in dramatically reduced surface roughness.TABLE 3 Run Ra Ra Run Abrasive Force time (start) (final) MRR # H₂OSize/Type Conc Qxidizer Conc RPM (PSI) (Hrs) (Å) (Å) (um/hr) 28 0/40%Al₂O₃200A 40% H2O2 20% 60 5 8 16.5 3.0 0.300 0.1 um diamond-10% 29 0/40%Al₂O₃200A 40% H2O2 20% 60 5 8 6.6 4.3 0.150 0.1 um diamond-10% 30 0/40%Al₂O₃200A 40% H2O2 20% 60 5 12 7.4 4.0 0.300 0.1 um diamond-10% 31 0/45%Al₂O₃200A 45% H2O2 10% 60 5 10 7.0 2.5 0.400 32 0/45% Al₂O₃200A 45% H2O210% 60 5 10 8 2.7 0.200 33 0/47.5% Al₂O₃200A 47.5% H2O2  5% 60 5 9 7 2.50.200 34 0/47.5% Al₂O₃200A 47.5% H2O2  5% 60 5 10 12.0 2.5 0.150

One specific embodiment of the invention provides a polishing mixturecomprising 180 ml of 200 Å alumina, 180 ml of de-ionized water, and 40ml of 30% hydrogen peroxide. Another specific embodiment of theinvention provides a polishing mixture comprising 150 ml of 200 Åalumina, 150 ml of de-ionized water, and 150 ml of 30% hydrogenperoxide.

Each of these specific embodiments was prepared by mixing theingredients using a magnetic stirrer for approximately 20 minutes. Acidwas not added to these specific embodiments.

The polishing mixture was then applied to a perforated polishing pad(e.g., a Rodel IC 1000 perforated pad) that had been conditioned with adiamond-conditioning ring for about 10 minutes before use. The aluminaabrasive used in these two specific embodiments above was colloidal, andincluded a combination of boehmite and corundum.

The polishing mixture was introduced into the perforated pad using aconventional spray system and worked into the pad for about 5 minuteswith a ceramic ring to ensure even distribution of the slurry throughoutthe pad.

Then test example wafers were respectively applied to the pad with adownward vertical force to a pressure of about 7 psi with the polishingmachine running at a speed of about 60 RPM. The introducing spray systemwas adjusted to provide about 1 ml of polishing mixture every 60seconds. An initial polishing run cycle time was established at twohours. Test example wafer surfaces were inspected at the end of two hourcycles using a ZYGO white light interferometer and surface roughness wasdetermined.

Typical initial wafer surface roughness following a conventionaldiamond-polishing process was measured at around 7 Å Ra. Following afirst polishing cycle using the improved polishing process, such aseither one of the two specific embodiments noted above, surfaceroughness was measured at around 4 Å Ra. Some scratches remain visiblefollowing the first cycle of the improved polishing process. Additionalcycles of the improved polishing process were performed until the testexample wafer surfaces were generally free from scratches and possesseda surface roughness below 3 Å Ra.

In general, rates of material removal for the improved polishing processvaried between 100 and 300 nm per cycle. Cycle times may be decreased asthe scratches are removed. Also more frequent inspections of the wafersurface may be required as the wafer nears the end of its polishingprocess. During the wafer polishing process, it is important that theedges of the wafers be regularly inspected to ensure that they maintaintheir initial chamfer. Any portion of the wafer breaking away from theedge will seriously impact its surface finish.

The improved polishing process may be applied in a manner consistentwith the techniques described in U.S. Pat. No. 5,584,898, the subjectmatter of which is hereby incorporated by reference. That is, apolishing mixture consistent with one or more embodiments of theinvention may find ready application within the system proposed by U.S.Pat. No. 5,584,898.

The attached figures contain color images illustrating the results ofvarious embodiments of the invention as applied to SiC wafers. Theillustrated results are only exemplary, but serve to dramaticallydistinguish results obtained from conventional CMP processes.

For example, FIGS. 1A through 1D are ZYGO images sequentiallyillustrating one test example as it passes through four (4) cycles ofthe improved polishing process according to one embodiment of theinvention. FIGS. 1A through 1D correspond to test example #31 shown inTable 3.

FIG. 1A shows an initial wafer surface following completion of aconventional diamond polishing process. This wafer surface has anaverage roughness of 7.01 Å Ra, and peak-to-valley roughness of 66.4 ÅPV. However, following the first improved polishing process cycle and asshown in FIG. 1B, the average roughness has been reduced to 4.42 Å Ra,and the peak-to-valley roughness has been reduced to 58.8 Å PV.Selective material removal was not observed. Subsequent to the secondand third improved polishing process cycles and as shown in FIG. 1C, theaverage roughness of the wafer surface has been reduced to 2.79 Å Ra.Finally, following a fourth improved polishing process cycle and asshown in FIG. 1D, a final average roughness of 2.56 Å Ra, and a finalpeak-to-valley roughness of 46.5 Å PV were obtained. As may be readilyseen from this sequence of images, the deep scratches and surfacedefects so apparent in FIGS. 1A and 1B are all but removed following thefourth improved polishing process cycle.

In contrast, FIGS. 2A through 2D are ZYGO images obtained sequentiallyduring a four (4) cycle application of a conventional CMP method usingcolloidal silica as an abrasive and having a pH higher than 11. Theseimages clearly show selective material removal from portions of thewafer surface around the scratches. This type of selectivity is a veryserious problem associated with the conventional CMP process. Beginningwith an average roughness of 30.4 Å Ra, and a peak-to-valley roughnessof 378 Å PV, four cycles of the conventional CMP process actuallydegrade the average roughness of the wafer surface to 42.7 Å Ra, and thepeak-to-valley roughness to 481 Å Pv.

FIG. 3 is a TEM image of the surface of a typical, commerciallyavailable wafer. Here, the scratch density is about 7.5×10⁴/cm², lineardislocation density is about 17.5×10⁴/cm², dislocation density at thesubsurface is about 1.3×10¹⁰/cm², and the longest dislocation length isabout 325 nm. By way of comparison, FIG. 4 is a TEM image of a similarwafer surface after polishing using the improved polishing processaccording to one embodiment of the invention. Here, the scratch densityis about 3.5*10⁴/cm², linear dislocation density is about 12.5×10⁴/cm²dislocation density at the subsurface is about 4.4×1 0⁷/cm², and thelongest dislocation length observed is about 300 nm.

FIGS. 5A and 5B are AFM images respectively illustrating polished SiCwafer surfaces. FIG. 5A shows the surface of a typical, commerciallyavailable SiC wafer after conventional CMP polishing. This surface ischaracterized by an average roughness of 1.8 nm Ra, and a root meansquare roughness of 2.8 nm Rq. However, FIG. 5B shows the surface of asimilar SiC wafer after polishing with the improved polishing processaccording to one embodiment of the invention. In contrast to the resultsshown in FIG. 5A, the wafer surface shown in FIG. 5B is characterized byan average roughness of 0.3 nm Ra, and a root mean square roughness of0.4 nm Rq.

FIGS. 6A and 6B are optical micrographs showing epitaxial galliumnitride layers grown on polished SiC wafers. (Of note, the circularfeatures visible in these micrographs are actually growth inducedhillocks not subsurface damage).

FIG. 6A shows the surface of a GaN layer grown on a typical,commercially available wafer having an average roughness of about 7.2 nmRa and a root mean square roughness of about 8.4 nm Rq. In contrast,FIG. 6B shows the surface of a GaN layer grown on a similar wafer afterpolishing with the improved polishing process according to oneembodiment of the invention, and having an average roughness of about4.3 nm Ra and a root mean square roughness of about 5.2 nm Rq.

FIGS. 7A though 7E are also AFM images showing the quality of epitaxialGaN layers grown on polished SiC substrates. FIG. 7A shows an AFM imageof an epitaxial GaN layer grown on a conventionally polished wafer.Here, Ra is about 7.2 nm, and Rq is about 8.4 nm. FIG. 7B shows an AFMimage of an epitaxial GaN layer grown on a SiC substrate polished usingthe improved polishing process. Here, Ra is about 4.3 nm, and Rq isabout 5.2 nm. Since the surface roughness of an epitaxial GaN layergrown on SiC substrate polished using the improved polishing process isconsiderably less than the surface roughness of a similar layer grown ona conventional substrate, semiconductor devices subsequently formed onthe GaN layer will enjoy advantageous performance properties and reduceddefect densities.

FIGS. 7C though 7E are AFM images of GaN epilayers grown on SiCsubstrates polished using the improved polishing process according toone embodiment of the invention. Each of the respective GaN epilayershas a thickness of about 1 micron, but the respective AFM images shownSiC substrates with varying thicknesses of material removed prior to theformation of the GaN epilayer. For example, FIG. 7C shows a SiC waferhaving 60 nm of material removed by the improved polishing process. Theaverage roughness of the subsequently formed GaN epilayer is about 3.4nm Ra. By way of comparison, FIGS. 7D and 7E show respective SiC wafershaving 250 nm and 1000 nm of material removed by the improved polishingprocess. The average roughness of the subsequently formed GaN epilayersis respectively about 1.2 nm Ra and 2.1 nm Ra. All of the SiC wafersshown in FIGS. 7A through 7E were selected from the same growth run of a4H—SiC on-axis material.

FIG. 8 is an AFM image showing a 5 μm×5 μm area near the center of a4H—SiC wafer (80 off-axis) following surface treatment using theimproved polishing process according to one embodiment of the invention.The wafer surface is very smooth having a low root-mean-square roughnessvalue of about 0.16 nm Rq.

In similar vein, FIG. 9 is an AFM image showing 5 μm×5 μm area near thecenter of a 6H—SiC wafer (on-axis). The wafer surface is also smoothhaving a root-mean-square roughness value of about 0.73 nm Rq.

FIGS. 10A and 10B are images corresponding to PBS measurements ofsubsurface damage for respective SiC wafers. The PBS measurements weremade using a probe beam developed from a 15 mW HeCd laser having anoperational wavelength of 325 nm formed within a 0.4 mm diameter spot onthe surface of the test sample wafers. FIG. 10A shows the subsurfacedamage observed in a 4H—SiC wafer as received from a commercial vendor(i.e., prior to application of the improved polishing process). Somestreakiness is observed in this image having an average scatter of 391ppm/sr. FIG. 10B shows the subsurface damage observed on a 4H—SiC waferfollowing surface treatment using the improved polishing process. Thewafer surface after polishing with the improved polishing processexhibited a significantly lower average scatter of 16 ppm/sr, but thereis some non-uniformity across the wafer surface. In particular, thescatter is low across about two-thirds of the wafer but is relativelyhigher across the remaining third. Yet, even the relatively higherscatter levels are far lower than seen from the conventionally providedwafer.

FIG. 11 is a TEM image showing a substrate prepared using a conventionalpolishing process. The errantly selective nature of this process removesonly heavily damaged portions of the wafer surface in close proximity ofscratches. Many longer dislocation loops remain. Thus, while there isreduced overall surface damage, there is also increased surfaceroughness. Note that the scale bar provided with the FIG. 11 is 500 nm.

FIG. 12 shows another substrate after polishing using the improvedpolishing process according to one embodiment of the invention. Thisembodiment first applies a conventional CMP process using 0.25 microndiamond grit. Thereafter, the wafer surface was polished through four(4) hours of one embodiment of the improved polishing process using apolishing mixture comprising; 180 ml of 200 A alumina, 180 ml ofde-ionized water, and 40 ml of 30% hydrogen peroxide. FIG. 12 is a planview TEM image, with contrast due to TEM sample thickness changes,showing no defects in the field of view. Higher uniform removal ratesleave no intrinsic damage detectable by TEM. There are no visibledislocations, and surface roughness is improved.

Of further note, the improved polishing process according to one or moreembodiments of the invention may be used to reclaim (e.g., re-surface)wafers having defective epitaxial layers. The improved polishing processmay also be applied to re-polish wafers having an undesirable surfacefinish. The improved polishing process may also be used as a replacementfor one or more steps in a conventional CMP process. Variably sizedabrasive (e.g., alumina) particles may be used between cycles of theimproved polishing process.

Any of these possible applications may be made to 6H— or 4H—SiC,conductive or semi-insulating, as well as on axis or off-axis wafertypes. The improved polishing process may be applied to a carbon-facedSiC wafer, a silicon-faced SiC wafer or a non-polar SiC wafer. (Anon-polar SiC wafer is a wafer that does not terminate in either acarbon face or a silicon and may be obtained, for example, by slicing aSiC boule in a direction non-perpendicular to its vertical growth axis).

In many of the foregoing embodiments, alumina is used as an abrasivewithin the polishing mixture. Indeed, alumina has proven to be veryeffective in many applications. Yet, other abrasives may be used,alternatively or in combination with alumina, and still other abrasivesor combination of abrasives may well prove more effective in certainapplications of the invention. The various polishing mixtures consistentwith the dictates of the invention may, optionally, comprise additivesthat reduce aggregation of the constituent abrasive particles.

Other abrasives adapted for use in various embodiments of the inventionmay include; oxides—such as alumina, other metal oxide, zirconia,silica, etc.—, diamond, carbides, nitrides (such as boron nitride), andother inorganic materials. Selected illustrative abrasive examplesinclude 2 μm zirconia, 1 μm and 0.1 μm alumina, and 0.1 μm and 0.05 μmdiamond. Oxide abrasives may include silicates, such as metal silicates.Other possible abrasives include mineral-derived abrasives.

Abrasives may be included in a polishing mixture consistent with theimproved polishing process in particles form. The size (e.g., diameteror other size parameter) of the abrasive particles may vary from betweennano-sized (e.g. 50 to 999 nm) to micron-sized (e.g., 1 to 10 microns),or even greater.

Use of an appropriately selected polishing mixture in accordance withone or more embodiments of the invention may allow elimination of theuse of diamond and/or colloidal silica from another conventionalpolishing process applied to the surface treatment of a wafer.Additionally, oxidizers may be added to increase the rate of materialremoval, for example, during the early polishing cycles of amultiple-cycle, improved polishing process.

The abrasive selected for use in the improved polishing process may haveoxidizer properties and may, therefore, function as both an oxidizer andabrasive within the polishing mixture.

Various oxidizers may be used to improve the performance of the improvedpolishing mixture consistent with one or more embodiments of theinvention. Exemplary oxidizers include: ozone-treated (i.e., ozonated)water, colloidal silica, hypochlorite (such as sodium hypochlorite), andperoxide (such as hydrogen peroxide), sulfates, phosphates, carbonates,percarbonates, other oxides, etc. A selected oxidizer may also havecertain abrasive qualities and may, therefore, function as both anoxidizer and abrasive.

The foregoing embodiments of the invention provide a substantiallydamage-free wafer surface adapted for use as a substrate. Suchsubstrates may be obtained at working temperatures well below thoseproposed for conventional CMP processes. For example, embodiments of theimproved polishing process may be run at temperatures ranging from roomtemperature up to 100C.

Substrates provided by the improved polishing process will find manypractical applications within semiconductor devices. That is, activesemiconductor devices formed on such substrates will exhibit improveddevice reliability and higher device yields at lower fabrication costs.Polishing induced dislocation densities will be significantly reducedover conventional substrates, in some cases being reduced by about threeorders of magnitude. Such defect densities approach native defectdensities present in the constituent material forming the substrate.Hence, the quality of wafer surface polishing will no longer be apotentially limiting factor in semiconductor device performance.

Embodiments of the invention are well suited to the polishing ofboule-grown SiC and epitaxially formed SiC. Embodiments of the inventionare also well suited to the polishing of other materials adapted for useas a substrate. These other materials include, for example, conductive,semiconductor, wide-bandgap semiconductor, semi-insulating, andinsulating types of materials, as well as combination thereof.

Thus, devices and layers susceptible to successful formation on any oneof the foregoing substrate types, as polished by the improved polishingprocess according to one or more embodiments of the invention, include;active semiconductor, including nitride semiconductor (such as GaN, AlN,AlGaN, etc.), other semiconductor layers and devices (such as arsenide,e.g., GaAs), phosphide (such as InP, GaP), oxides (such as SnO₂), and/orternary semiconductor (such as AlGaN for all Al_(x)Ga_(1-x)N, where x isbetween 0 and 1).

Devices having improved performance characteristics may be formed on athin film of aluminum nitride, gallium nitride, or silicon carbide, asformed on a substrate polished using the improved polishing process.That is, polished substrates provided by embodiments of the inventionare particularly well adapted to support the subsequent growth ofepitaxial films. In turn, these epitaxial films support the formation ofactive layers and/or devices, because the damage resulting from thefabrication and polishing of the constituent wafer surface that soregularly degrades the performance of devices formed on conventionallyprepared substrates simply does not exist in a substrate polished usingthe improved polishing process.

Substrates formed from a wafer having a surface polished using theimproved polishing process according to one or more embodiments of theinvention may be used to support other devices such as reflectors,interferometric devices—such as antireflection films, windows, filters,RF devices, IR devices, optical devices, UV devices, or X-ray devices,and other apparatus requiring a polished surface, e.g., computer disksor disk drives.

Similarly, the improved polishing process provides improved substratesadapted to support High Electron Mobility Transistors, e.g., AlGaN/GaNHEMT, since improvements may be realized in the transport properties,including uniformity, and RF performance of such devices. Otherexemplary devices supported by the improved substrates provided byembodiments of the invention include lasers, other light emittingdevices such as light emitting diodes (LEDs)—where the term “light”generally denotes electromagnetic radiation in the infrared, visible,and ultraviolet spectral ranges, radar devices, low-loss power switchingdevices and systems, cryogenic devices (such as nitride-based cryogenicelectronic devices), transistors, amplifiers (such as low noiseamplifiers), integrated circuits, and devices adapted for use inelectric vehicles. Some devices and/or layers formed on substratespolished using the improved polishing process are particularly wellsuited for use in hostile environments like space.

As evidenced from the foregoing example, the improved polishing processprovided by one or more embodiments of the invention is non-selectiverelative to scratches and other wafer surface defects. As a result,scratches and other surface defects are polished out of the workingsurface of a wafer, instead of being polish-propagated down through theworking surface as is common with conventional CMP processes.Additionally, the improved polishing process prevents and/or removessubsurface damage from a wafer being polished. Nonetheless, the improvedpolishing process is also characterized in many embodiments by a rate ofmaterial removal equal to or greater than that produced by conventionalpolishing processes. The dislocation density (e.g., 10⁶ cm⁻²dislocations or less) introduced by the improved polishing process isapproximately equal to the dislocation density reported for high qualityGaN and SiC layers. Thus, where a SiC substrate is polished using theimproved polishing process, the quality of a subsequently formedepitaxial layer, such as a GaN layer, will not be limited by the surfacefinish of the SiC substrate.

The improved polishing process may be used exclusively within thesurface treatment of a wafer surface, or it may be used as one (e.g., afinal) or more process components in a surface treatment potentiallycomprising a conventional mechanical, CMP, and/or etching process(es).However, used in the overall process of treating a material surface(e.g., a substrate), the improved polishing process allows lower costdevices to be fabricated with higher yield and fewer defects. Since theimproved polishing process provides repeatable surface roughness, a highrate of material removal with low resulting damage, and reducedsubsurface damage, consistent substrate finishing may be achieved andaccounted for in the design of epitaxial layers and/or devicessubsequently formed on the substrate. This consistent, controllablesubstrate finishing further allows the improved polishing process to beapplied effectively to both wafer surfaces and an epitaxial layer grownon a wafer surface. The polished surfaces provided by the improvedpolishing process may be planar, or in some examples, curved in nature.

The invention is not restricted to the examples and embodimentsdescribed above. Such teaching examples are not intended as limitationson the scope of the invention. Processes, apparatus, compositions, andthe like described herein are exemplary and not intended as limitationson the scope of the invention. Changes therein and other uses will occurto those skilled in the art. The scope of the invention is defined bythe following claims.

1. A process for treating a surface of a material, comprising: polishingthe surface using a polishing mixture having a pH of seven (7) or less,wherein the polishing mixture comprises; an abrasive and an oxidizer. 2.The process of claim 1, wherein the surface comprises a scratch andwherein the polishing mixture is non-selective relative to the scratch.3. The process of claim 2, wherein the abrasive has a hardness less thanthe material.
 4. The process of claim 3, wherein the abrasive comprisesat least one of alumina and colloidal alumina.
 5. The process of claim2, wherein the polishing mixture has a pH equal to or less than five(5).
 6. The process of claim 1, wherein the material comprises at leastone a conducting, insulating, dielectric or semi-conducting materialselected from a group of materials consisting essentially of; a metal,an oxide, a glass, an alloy, a carbide, a nitride, diamond, a silicide,a chromide, ferride, a boride, a sulfide, a phosphide, silicon nitride,silicon nitride, aluminum nitride, gallium nitride, alumina-galliumnitride, indium-gallium nitride, Safire, Indium phosphide, boronnitride, silicon, and silica.
 7. The process of claim 6, wherein thematerial comprises silicon carbide terminated in a silicon face, acarbon face, or a non-polar face.
 8. The process of clam 6 wherein theabrasive comprises at least one of alumina, a metal oxide, zirconia,silica, diamond, a carbide, and a nitride.
 9. The process of claim 8,wherein the abrasive has a size ranging from between several nanometersto one micron.
 10. The process of claim 8, wherein the oxidizercomprises at least one of ozone-treated water, colloidal silica, ahypochlorite, a peroxide, a sulfate, a phosphate, a carbonate, apercarbonate, and an oxide.
 11. A polishing mixture comprising: anabrasive and an oxidizer mixed in an acidic solution having a pH lessthan or equal to seven (7).
 12. The polishing mixture of claim 11,wherein the polishing mixture comprises a non-silica abrasive and has apH less than or equal to five (5).
 13. The polishing mixture of claim11, wherein the abrasive has a Mohs hardness less than or equal to nine(9).
 14. The polishing mixture of claim 13, wherein the abrasivecomprises colloidal alumina.
 15. The polishing mixture of claim 11,wherein the acidic solution comprises water and an acid.
 16. A processof fabricating a semiconductor device comprising: polishing a surface ofa material wafer using a non-selective polishing mixture having a pH ofseven (7) or less and comprising an abrasive and an oxidizer; and,forming at least one of a homo-epitaxial layer, a hetro-epitaxial layer,a dielectric layer, and a conductive layer on the substrate.
 17. Theprocess of claim 16, wherein the material comprises silicon carbide andthe epitaxial layer comprises a nitride semiconductor layer or a siliconcarbide layer.
 18. The process of claim 16, wherein the polishingmixture has a pH about five (5) and the abrasive comprises colloidalalumina.
 19. The process of claim 16, wherein the material comprises atleast one a conducting, insulating, dielectric or semi-conductingmaterial selected from a group of materials consisting essentially of; ametal, an oxide, a glass, an alloy, a carbide, a nitride, diamond, asilicide, a chromide, ferride, a boride, a sulfide, a phosphide, siliconnitride, silicon nitride, aluminum nitride, gallium nitride,alumina-gallium nitride, indium-gallium nitride, Safire, Indiumphosphide, boron nitride, silicon, and silica; wherein the abrasivecomprises at least one abrasive selected from a group of abrasivesconsisting essentially of; diamond, an oxide, a metal oxide, a carbide,a nitride, a silicate, and a metal silicate; and, wherein the oxidizercomprises at least one oxidizer selected from a group of oxidizersconsisting essentially of; ozone-treated water, colloidal silica, ahypoclorite, a peroxide, a sulfate, a phosphate, a carbonate, and apercarbonate.
 20. The process of claim 16, wherein polishing the surfaceof the material wafer comprises: polishing the surface of the materialwafer using a mechanical polishing process or a chemical-mechanicalpolishing (CMP) process using diamond or colloidal silica; andthereafter, polishing the surface of the material wafer at a temperatureless than 100° C. using the polishing mixture.
 21. The process of claim20, wherein polishing the surface of the material wafer takes place atroom temperature.
 22. The process of claim 16, further comprising: afterpolishing the surface of the material wafer, patterning the surface ofthe wafer, or implanting ions into the surface of the wafer.